General info:
LDAT is the Intel array test port, it is used for manufacturing
validation of arrays in their product. Examples of these arrays are
the caches, the microcode stores and the various buffers inside the
CPU core.
Procedure to read:
Load SDAT
Load PDAT with command A1 set to READ, others set to NOP
Read DatOut
Procedure to write:
Write DatIn
Load SDAT
Load PDAT with command A1 set to WRITE, others set to NOP
Undefined bits are set to 0.
Mode (Mod) defaults to 1 for both READ and WRITE
Other fields default to 0/NOP.
BDX Broadwell-X:
From Intel System Studio 2014 XML Database
Port offsets (Normal):
PDAT +0
DatOut +2
DatIn +3 + Index
SDAT +4 #Not sure if 1 or 4
SDAT Bitfield:
3 2 1 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+-----------+---+---------+---+-----------+-------+
| Port |Mod| DWord | | ArraySel |BankSel|
+-----------+---+---------+---+-----------+-------+
PDAT Bitfield:
3 2 1 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+---+---+---+---+---+---+---------------+-----------------------+
| C1| C0| B1| B0| A1| A0| | FastAddr |
+---+---+---+---+---+---+---------------+-----------------------+
Port offsets (Legacy):
PDAT 0
DatOut 8
SDAT 4 #Not sure if 1 or 4
PDAT Bitfield:
3 2 1 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+-----------+---+-------+---+---------+-+-------+
| Port |Mod| DWord | |ArraySel | |BankSel|
+-----------+---+-------+---+---------+-+-------+
SDAT Bitfield:
3 2 1 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+---+---+---+---+---+---+---------------+-----------------------+
| C1| C0| B1| B0| A1| A0| | FastAddr |
+---+---+---+---+---+---+---------------+-----------------------+
Command fields:
| Encoding | Name |
+----------+-----------------+
| 0 | NOP |
| 1 | RDIGN |
| 2 | WRITE |
| 3 | READ/WRITEBAR |
SNB Sandy Bridge:
From Intel System Studio 2014 XML Database
Port offsets:
PDAT +0
SDAT +1
DatOut +2
DatIn +3 + Index
SDAT Bitfield:
3 2 1 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+-----------+---+-------+---+---------+-+-------+
| Port |Mod| DWord | |ArraySel | |BankSel|
+-----------+---+-------+---+---------+-+-------+
PDAT Bitfield:
3 2 1 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+---+---+---+---+---+-------------------+-----------------------+
| C1| | B1| | A1| | FastAddr |
+---+---+---+---+---+-------------------+-----------------------+
Command fields:
| Encoding | Name |
+----------+--------+
| 0 | NOP |
| 1 | RDIGN |
| 2 | WRITE |
| 3 | READ |
Known arrays:
| PDAT CR | ArraySel | Name | Description |
+---------+-----------+------------------+---------------------------------|
| 0x359 | 0 | dsbofset | DSB FE OFFSET array |
| 0x359 | 1 | dsbnata | DSB FE NATA array |
| 0x359 | 2 | dsbnata | DSB FE PFRQ array |
| 0x359 | 6 | dsbofset | DSB FE TAG array |
| 0x361 | 2+2*Table | jws_pred_global | The BPU global predictors |
| 0x361 | 8 | bp_l2bpu set0 | The level 2 BPU predictor,set 0 |
| 0x361 | 9 | bp_l2bpu set1 | The level 2 BPU predictor,set 1 |
| 0x361 | 10 | bp_target(tag) | BIT TargetTAG array (even) |
| 0x361 | 11 | bp_target(tag) | BIT TargetTAG array (odd) |
| 0x361 | 12 | bp_target(tag) | BIT TargetTAG array (indirect) |
| 0x361 | 13 | bp_target(addr) | BIT TargetAddr array (even) |
| 0x361 | 14 | bp_target(addr) | BIT TargetAddr array (odd) |
| 0x361 | 15 | bp_target(addr) | BIT TargetAddr array (indirect) |
| 0x361 | 17 | bp_bit | The main BPU target&tag array |
| 0x361 | 18 | bp_baq | BAQBRD? |
| 0x361 | 19 | bpq | Branch Predict Queue |
| 0x377 | 2 | dl1_cache(data) | L1D Cache Data array |
| 0x377 | 3 | dl1_cache(mesi) | L1D Cache ?MESI? array |
| 0x377 | 5 | dl1_cache(tag) | L1D Cache Tag array |
| 0x377 | 6 | dl1_cache(lru) | L1D Cache LRU array |
| 0x387 | 0 | il1_cache(data) | L1I Cache Data array |
| 0x387 | 1 | il1_victim(data) | L1I Victim Cache Data array |
| 0x387 | 2 | il1_victim(tag) | L1I Victim Cache Tag array |
| 0x387 | 3 | il1_cache(tag) | L1I Cache Tag array |
| 0x387 | 4 | il1_cache(flags) | L1I Cache Flags array |
| 0x387 | 5 | itlb_sm_st | ITLB Small Page, SingleThread |
| 0x3CE | 4 | mob_disambig | Memory disambiguation predict |
| 0x3CE | 0,1 | mob_lb | MOB Load Buffer |
| 0x3CE | 2,3,5 | mob_sab | MOB Store Address Buffer |
| 0x3CE | 6 | mob_phy | MOB Physical Address Buffer |
| 0x3D3 | 0 | id_esp_data | Instruction ESP data Q |
| 0x3D3 | 3 | MS RAM | The MS patch RAM |
| 0x3E4 | 0 | rob_wbac | ROB Ready bits and flags |
| 0x3E4 | 1 | rob_al | ROB ALLOC Array |
| 0x3E4 | 2 | bob_wbac | Branch order buffer Writeback |
| 0x3E4 | 3 | non_renamed | Non-renamed retirement array |
| 0x3EC | 5 | dtlb_sm_tag | DTLB Small Page Tag |
I will add more of these later ( no later than 24/05/2020 )
HSW Haswell:
PDAT Names:
| CRB Addr| Name |
+---------+---------------------|
| 0x361 | BPU1_CR_PDAT |
| 0x359 | DSBFE_CR_PDAT |
| 0x366 | CORE_CR_PDAT |
| 0x377 | DCU_CR_PDAT |
| 0x382 | IESLOW_CR_PDAT |
| 0x393 | MI_CR_PDAT |
| 0x3A9 | ML2_CR_PDAT |
| 0x3CE | MOB_CR_PDAT |
| 0x3D3 | MS_CR_PDAT |
| 0x3EC | PMH_CR_PDAT |
| 0x3F6 | RAT_CR_PDAT |
| 0x3FA | AL_CR_PDAT |
GLM Goldmont:
Reverse engineered from https://github.com/chip-red-pill/crbus_scripts
Port offsets:
PDAT +0
SDAT +1
DatOut +2
DatIn +4,5? + Index
SDAT Bitfield:
3 2 1 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+-----------+---+-------+-------+-------+-------+
| Port |Mod| DWord |ArrySel| |BankSel|
+-----------+---+-------+-------+-------+-------+
PDAT Bitfield:
3 2 1 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+---------------+---+-----------+-------------------------------+
| | A1| | FastAddr |
+---------------+---+-----------+-------------------------------+
Command fields:
| Encoding | Name |
+----------+--------+
| 0 | NOP |
| 2 | WRITE |
| 3 | READ |
Known arrays:
| PDAT CR | ArraySel | Name | Description |
+---------+-----------+------------------+---------------------------------|
| 0x6A0 | 0 | ms_rom | Microcode ROM |
| 0x6A0 | 1 | ms_irom | Microcode constant ROM |
| 0x6A0 | 2 | ms_iram | Microcode update constant RAM |
| 0x6A0 | 3 | ms_match_patch | Microcode update match/patch |
| 0x6A0 | 4 | ms_ram | Microcode update RAM |